1. Field of the Invention
The present invention is directed to a phase-locked loop for controlling the phase of an output signal S2 dependent on a reference signal S1.
2. Description of the Prior Art
FIG. 4 shows a block circuit diagram of a known, digital phase-locked loop (PLL) of the above type. By comparison in a phase detector 26, the phase position of the output signal S2 having the frequency f2 is regulated to the phase of the reference signal S1 having the frequency f2. The follow-up of the output signal S2, however, is not error-free. The phase timing error x(t), i.e. the phase difference between the reference signal S1 and the output signal S2, is established in digital phase-locked loops by the cycle duration or quantization stage T2=1/f2 of the output signal, which, as indicated in FIG. 4 by arrow lines, is also employed as the clock frequency for the digital components such as the dividers 24, 27, the phase detector 26 of the integrator 28 and the digital-to-analog converter 30.
The reason why a phase timing error arises in the phase-locked loop shown in FIG. 4 is explained below on the basis of FIGS. 5, 6A, 6B and 6C.
The phase positions of the signals S2, S2M (output signal at the input of the phase detector divided by M) and S2N (reference signal at the input of the phase detector divided by N) relative to the reference signal S1 are shown at different, successive times t0 (FIG. 6A), t1 (FIG. 6B) and t2 (FIG. 6C). A slighter higher eigenfrequency (leading phase position) of the crystal oscillator 31 is assumed. The (higher-frequency) signal S2 samples the phase of the reference signal S1 with a cycle T2=1/f2 (symbolized in FIGS. 6A through 6C by a vertical arrow). When the phase shift of the signals S1 and S2 relative to one another exceeds the cycle duration T2, then this is acquired by the phase detector 26 and the voltage-controlled oscillator 31 is controlled with the integrator 28, the summing circuit 29 and the digital-to-analog converter 30, to correspondingly re-adjust the frequency of the signal, so that the phase shift between S1 and S2 is minimized. Within the cycle duration, however, the linking of the signals S1N, S2M and S2--which are synchronous relative to one another--to the reference signal S1 is cancelled. This dead time fundamentally arises due to the sampling of the reference signal S1 by the oscillator signal S2. Any drift of the oscillator 31 will not re-adjusted in this way during the dead time T2 and thus fully affects the output signal S2. The phase difference is acquired by the phase detector 26 only given a phase timing error x=T2, and the frequency of the oscillator 31 is correspondingly readjusted. A time-dependent phase timing error x(t) having a maximum value .DELTA.x=T2 thus occurs, the typical time curve thereof being shown in FIG. 5. One can recognize a typical delta or sawtooth-shaped curve that is first defined in the leading direction by the drift of the oscillator. When the error x(t) reaches the threshold T2, a lower locking voltage that reduces the frequency of the oscillator 31 is generated. The error x(t) then in turn becomes smaller until the phase detector 26 no longer acquires a phase difference, and the locking voltage at the oscillator subsequently disappears.
FIG. 6B shows the situation when a phase timing error 0.ltoreq.x.ltoreq.T2 exists between the signal S1 and the signals S2, S1N and S1M, which are synchronous relative to one another. When the phase timing error continues to increase until x=T2 has been reached (FIG. 6C), the sampling by the signal S2 acquires the changed phase position, and the oscillator is correspondingly re-adjusted.
An optimally small phase timing error is advantageous for specific applications such as, for instance, clock editing circuits in synchronous digital communication networks.
It is known to reduce the phase timing error x(t) by employing high-frequency, re-adjusted, controllable oscillators and to thus achieve a high frequency of the signal S2. This method, however, has the disadvantage that the operating range of a voltage-controlled crystal oscillator (VCXO) decreases with the square of the harmonic of the crystal oscillator that is employed, i.e., the range of control of the oscillator frequency becomes smaller as the operating frequency of the crystal oscillator becomes higher relative to the fundamental oscillation thereof. For output signals of higher frequency S2, moreover, the digital components of the phase-locked loop must be realized with fast logic circuits, causing an increase in cost and power consumption. Due to the high number of synchronously clocked flip-flops in counters and dividers, the operating frequency is considerably lower than the limit frequency of, for example, a flip-flop. In one example with 500 synchronous flip-flops, an operating frequency of only 50 MHZ could be achieved with 0.5 .mu.m CMOS technology, corresponding to a phase timing error of approximately 20 ns.